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sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 sn74ahc1g14 single schmitt-trigger inverter gate 1 features 3 description the sn74ahc1g14 device is a single inverter gate. 1 ? operating range 2 v to 5.5 v the device performs the boolean function ? maximum t pd of 10 ns at 5 v y = a. ? low power consumption, 10- a max i cc the device functions as an independent inverter gate, ? 8-ma output drive at 5 v but because of the schmitt action, gates may have ? latch-up performance exceeds 250 ma per different input threshold levels for positive- (v t+ ) and jesd 17 negative-going (v t ? ) signals. device information 2 applications order number package (pin) body size (nom) ? barcode scanners SN74AHC1G14DBV sot-23 (5) 2.90 mm 1.60 mm ? cable solutions sn74ahc1g14dck sc70 (5) 2.00 mm 1.25 mm ? e-books sn74ahc1g14drl sot (5) 1.60 mm 1.20 mm ? embedded pcs (1) for all available packages, see the orderable addendum at ? field transmitter: temperature or pressure the end of the data sheet. sensors logic diagram (positive side) ? fingerprint biometrics ? hvac: heating, ventilating, and air conditioning ? network-attached storage (nas) ? sever motherboard and psu ? software defined radios (sdr) ? tv: high definition (hdtv), lcd, and digital ? video communications systems ? wireless data access cards, headsets, keyboards, mice, and lan cards 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder a y 2 4 support &community tools & software technical documents sample &buy
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com table of contents 8.2 functional block diagram ......................................... 8 1 features .................................................................. 1 8.3 feature description ................................................... 8 2 applications ........................................................... 1 8.4 device functional modes .......................................... 8 3 description ............................................................. 1 9 application and implementation .......................... 9 4 revision history ..................................................... 2 9.1 application information .............................................. 9 5 pin configuration and functions ......................... 3 9.2 typical application ................................................... 9 6 specifications ......................................................... 4 10 power supply recommendations ..................... 11 6.1 absolute maximum ratings ...................................... 4 11 layout ................................................................... 11 6.2 esd ratings .............................................................. 4 11.1 layout guidelines ................................................. 11 6.3 recommended operating conditions ....................... 4 11.2 layout example .................................................... 11 6.4 thermal information .................................................. 5 12 device and documentation support ................. 12 6.5 electrical characteristics ........................................... 5 12.1 documentation support ........................................ 12 6.6 switching characteristics, v cc = 3.3 v 0.3 v ........ 6 12.2 community resources .......................................... 12 6.7 switching characteristics, v cc = 5 v 0.5 v ........... 6 12.3 trademarks ........................................................... 12 6.8 operating characteristics .......................................... 6 12.4 electrostatic discharge caution ............................ 12 6.9 typical characteristics .............................................. 6 12.5 glossary ................................................................ 12 7 parameter measurement information .................. 7 13 mechanical, packaging, and orderable 8 detailed description .............................................. 8 information ........................................................... 12 8.1 overview ................................................................... 8 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision p (august 2013) to revision q page ? added applications section, device information table, pin configuration and functions section, esd ratings table, thermal information table, typical characteristics section, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ..................................... 1 changes from revision o (may 2013) to revision p page ? updated document to new ti data sheet format - no specification changes ........................................................................ 1 changes from revision n (june 2005) to revision o page ? changed document format from quicksilver to doczone. ..................................................................................................... 1 2 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14
sn74ahc1g14 www.ti.com scls321q ? march 1996 ? revised september 2015 5 pin configuration and functions dbv package dck package 5-pin sot-23 5-pin sc70 top view top view drl package 5-pin sot top view pin functions (1) pin i/o description no. name 1 nc ? no connect 2 a i data input 3 gnd ? ground 4 y o data output 5 vcc ? power (1) nc ? no internal connection. copyright ? 1996 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: sn74ahc1g14 3 2 4 5 1 nc v cc y a gnd 2 4 5 1 nc v cc y a gnd 3 3 2 4 5 1 nc v cc y a gnd
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 7 v v i input voltage (2) ? 0.5 7 v v o output voltage (2) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 20 ma i ok output clamp current v o < 0 or v o > v cc 20 ma i o continuous output current v o = 0 to v cc 25 ma continuous current through v cc or gnd 50 ma t j maximum junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 1500 electrostatic v (esd) v discharge charged-device model (cdm), per jedec specification jesd22-c101, all pins (2) 1000 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage 2 5.5 v v i input voltage 0 5.5 v v o output voltage 0 v cc v v cc = 2 v ? 50 a i oh high-level output current v cc = 3.3 v 0.3 v ? 4 ma v cc = 5 v 0.5 v ? 8 v cc = 2 v 50 a i ol low-level output current v cc = 3.3 v 0.3 v 4 ma v cc = 5 v 0.5 v 8 t a operating free-air temperature ? 40 125 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , scba004 . 4 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14
sn74ahc1g14 www.ti.com scls321q ? march 1996 ? revised september 2015 6.4 thermal information sn74ahc1g14 thermal metric (1) dbv (sot-23) dck (sc70) drl (sot) unit 5 pins 5 pins 5 pins r ja junction-to-ambient thermal resistance 225.7 252 271.8 c/w r jc(top) junction-to-case (top) thermal resistance 160.3 ? 116.6 c/w r jb junction-to-board thermal resistance 59.4 ? 89.9 c/w jt junction-to-top characterization parameter 41.0 ? 17.3 c/w jb junction-to-board characterization parameter 58.7 ? 89.4 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics over operating free-air temperature range (unless otherwise noted) recommended t a = 25 c t a = ? 40 c to 85 c test t a = ? 40 c to 125 c parameter v cc unit conditions min typ max min typ max min typ max v t+ 3 v 1.2 2.2 1.2 2.2 1.2 2.2 positive-going 4.5 v 1.75 3.15 1.75 3.15 1.75 3.15 v input threshold 5.5 v 2.15 3.85 2.15 2.85 2.15 3.85 voltage v t ? 3 v 0.9 1.9 0.9 1.9 0.9 1.9 negative-going 4.5 v 1.35 2.75 1.35 2.75 1.35 2.75 v input threshold 5.5 v 1.65 3.35 1.65 3.35 1.65 3.35 voltage 3 v 0.3 1.2 0.3 1.2 0.25 1.2 v t hysteresis 4.5 v 0.4 1.4 0.4 1.4 0.35 1.4 v (v t+ ? v t ? ) 5.5 v 0.5 1.6 0.5 1.6 0.45 1.6 2 v 1.9 2 1.9 1.9 i oh = ? 50 a 3 v 2.9 3 2.9 2.9 v oh 4.5 v 4.4 4.5 4.4 4.4 v i oh = ? 4 ma 3 v 2.58 2.48 2.4 i ol = ? 8 ma 4.5 v 3.94 3.8 3.7 2 v 0.1 0.1 0.1 i oh = 50 a 3 v 0.1 0.1 0.1 v ol 4.5 v 0.1 0.1 0.1 v i oh = 4 ma 3 v 0.36 0.44 0.55 i ol = 8 ma 4.5 v 0.36 0.44 0.55 v i = 5.5 v or 0 v to i i 0.1 1 1 a gnd 5.5 v v i = v cc or i cc 5.5 v 1 10 10 a gnd, i o = 0 v i = v cc or c i 5 v 2 10 10 10 pf gnd copyright ? 1996 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: sn74ahc1g14
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com 6.6 switching characteristics, v cc = 3.3 v 0.3 v over recommended operating free-air temperature range (unless otherwise noted) (see figure 2 ) recommended t a = 25 c t a = ? 40 c to 85 c t a = ? 40 c to from to output parameter unit 125 c (input) (output) capacitance typ max min max min max t plh 8.3 12.8 1 15 1 16 ns a y c l = 15 pf t phl 8.3 12.8 1 15 1 16 ns t plh 10.8 16.3 1 18.5 1 19.5 ns a y c l = 50 pf t phl 10.8 16.3 1 18.5 1 19.5 ns 6.7 switching characteristics, v cc = 5 v 0.5 v over recommended operating free-air temperature range (unless otherwise noted) (see figure 2 ) recommended t a = ? 40 c to t a = 25 c t a = ? 40 c to from to output 85 c parameter unit 125 c (input) (output) capacitance typ max min max min max t plh 5.5 8.6 1 10 1 11 ns a or b y c l = 15 pf t phl 5.5 8.6 1 10 1 11 ns t plh 7 10.6 1 12 1 11 ns a or b y c l = 50 pf t phl 7 10.6 1 12 1 11 ns 6.8 operating characteristics v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance no load, f = 1 mhz 9 pf 6.9 typical characteristics t a = 25 c, v a = 5 v figure 1. response time vs output voltage 6 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14 0 1 2 3 4 5 0 5 10 15 20 25 30 35 40 45 50 signal voltage (v) time (ns) c001
sn74ahc1g14 www.ti.com scls321q ? march 1996 ? revised september 2015 7 parameter measurement information a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 , t r 3 ns, t f 3 ns. d. the outputs are measured one at a time with one input transition per measurement. e. all parameters and waveforms are not applicable to all devices. figure 2. load circuit and voltage waveforms copyright ? 1996 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: sn74ahc1g14 50% v cc v cc v cc 0 v0 v t h t su voltage waveforms setup and hold times data input t plh t phl t phl t plh v oh v oh v ol v ol v cc 0 v 50% v cc 50% v cc input out-of-phase output in-phase output timing input 50% v cc voltage waveforms propagation delay times inverting and noninverting outputs output control output waveform 1 s1 at v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc v ol + 0.3 v 50% v cc 0 v v cc voltage waveforms enable and disable times low- and high-level enabling t plh /t phl t plz /t pzl t phz /t pzh open drain open v cc gnd v cc test s1 v cc 0 v 50% v cc t w voltage waveforms pulse duration input from output under test c l (see note a) load circuit for 3-state and open-drain outputs s1 v cc r l = 1 k gnd from output under test c l (see note a) test point load circuit for totem-pole outputs open 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc v oh ? 0.3 v
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com 8 detailed description 8.1 overview the sn74ahc1g14 device is a single inverter gate. the device performs the boolean function y = a. the device functions as an independent inverter gate, but because of the schmitt action, gates may have different input threshold levels for positive- (v t+ ) and negative-going (v t ? ) signals. 8.2 functional block diagram figure 3. logic diagram (positive side) 8.3 feature description the sn74ahc1g14 device has a wide operating v cc range of 2 v to 5.5 v, which allows it to be used in a broad range of systems. the low propagation delay allows fast switching and higher speeds of operation. in addition, the low-power consumption makes this device a good choice for portable and battery power-sensitive applications. 8.4 device functional modes table 1 lists the functional modes for sn74ahc1g14. table 1. function table input a output y h l l h 8 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14 a y 2 4
sn74ahc1g14 www.ti.com scls321q ? march 1996 ? revised september 2015 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information physically interactive interface elements like push buttons or rotary knobs offer simple and easy ways to interact with an electronic system. many of these physical interface elements often have issues with bouncing, or where the physical conductive contact can connect and disconnect multiple times during a button push or release. this bouncing can cause one or more faulty transient signals to be passed during this transitional period. these faulty signals can be observed in many common applications, for example, a television remote with bouncing error can adjust the tv channel multiple times despite the button being pushed only once. to mitigate these faulty signals, we can use a schmitt-trigger, or a device with hysteresis, to remove these faulty signals. hysteresis allows a device to remember its history, and in this case, the sn74ahc1g14 uses this memory to debounce the signal of the physical element, or filter the faulty transient signals and pass only the valid signal each time the element is used. in this example, we show a push-button signal passed through an sn74ahc1g14 that is debounced and inverted to the microprocessor for push detection. 9.2 typical application figure 4. switch debouncer 9.2.1 design requirements the sn74ahc1g14 device uses cmos technology and has balanced output drive. take care to avoid bus contention because it can drive currents that would exceed maximum limits. the sn74ahc1g14 allows for performing logical boolean functions with hysteresis using digital signals. all input signals must remain as close as possible to either 0 v or vcc for optimal operation. copyright ? 1996 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: sn74ahc1g14 sn74ahc1g14 physical push button microprocessor v cc
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com typical application (continued) 9.2.2 detailed design procedure 1. recommended input conditions: ? for rise time and fall time specifications, see t/ v in the recommended operating conditions table. ? for specified high and low levels, see v ih and v il in the recommended operating conditions table. ? inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 v at any valid v cc . 2. recommended output conditions: ? load currents must not exceed 50 ma. 3. frequency selection criterion: ? the effects of frequency upon the power consumption of the device can be studied in cmos power consumption and cpd calculation , scaa035 . ? added trace resistance and capacitance can reduce maximum frequency capability; follow the layout practices listed in the layout guidelines section. 9.2.3 application curves v cc = 5.5 v v cc = 5.5 v figure 6. ahc family v ol vs i ol figure 5. ahc family v oh vs i oh 10 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14
sn74ahc1g14 www.ti.com scls321q ? march 1996 ? revised september 2015 10 power supply recommendations the power supply can be any voltage between the minimum and maximum supply voltage rating listed in the recommended operating conditions table. each v cc terminal must have a good bypass capacitor to prevent power disturbance. for devices with a single supply, a 0.1- f bypass capacitor is recommended. if multiple pins are labeled v cc , then a 0.01- f or 0.022- f capacitor is recommended for each v cc because the v cc pins are tied together internally. for devices with dual- supply pins operating at different voltages, for example v cc and v dd , a 0.1- f bypass capacitor is recommended for each supply pin. to reject different frequencies of noise, use multiple bypass capacitors in parallel. capacitors with values of 0.1 f and 1 f are commonly used in parallel. the bypass capacitor must be installed as close as possible to the power terminal for best results. 11 layout 11.1 layout guidelines reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. when a pcb trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance of the trace, which results in the reflection. not all pcb traces can be straight; therefore some traces must turn corners. figure 7 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. 11.2 layout example figure 7. trace example copyright ? 1996 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: sn74ahc1g14 worst better best 1w min. w 2w
sn74ahc1g14 scls321q ? march 1996 ? revised september 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? implications of slow or floating cmos inputs , scba004 ? cmos power consumption and cpd calculation , scaa035 ? selecting the right texas instruments signal switch , szza030 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser based versions of this data sheet, refer to the left hand navigation. 12 submit documentation feedback copyright ? 1996 ? 2015, texas instruments incorporated product folder links: sn74ahc1g14
package option addendum www.ti.com 26-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples SN74AHC1G14DBVr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (a143, a14g, a14j, a14l, a14s) SN74AHC1G14DBVre4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 a14g SN74AHC1G14DBVrg4 active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 a14g SN74AHC1G14DBVt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (a143, a14g, a14l, a14s) sn74ahc1g14dck3 active sc70 dck 5 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 afy sn74ahc1g14dckr active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (af3, afg, afj, af l, afs) sn74ahc1g14dckre4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 af3 sn74ahc1g14dckrg4 active sc70 dck 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 af3 sn74ahc1g14dckt active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (af3, afg, afj, af l, afs) sn74ahc1g14dckte4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 af3 sn74ahc1g14dcktg4 active sc70 dck 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 af3 sn74ahc1g14drlr active sot-5x3 drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 afs sn74ahc1g14drlrg4 active sot-5x3 drl 5 4000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 afs (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 26-sep-2018 addendum-page 2 (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74AHC1G14DBVr sot-23 dbv 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 q3 SN74AHC1G14DBVr sot-23 dbv 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 SN74AHC1G14DBVr sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 SN74AHC1G14DBVr sot-23 dbv 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 q3 SN74AHC1G14DBVrg4 sot-23 dbv 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 SN74AHC1G14DBVt sot-23 dbv 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 q3 SN74AHC1G14DBVt sot-23 dbv 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 q3 SN74AHC1G14DBVt sot-23 dbv 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 q3 sn74ahc1g14dckr sc70 dck 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74ahc1g14dckr sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahc1g14dckrg4 sc70 dck 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahc1g14dckt sc70 dck 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 q3 sn74ahc1g14dckt sc70 dck 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 q3 sn74ahc1g14dckt sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahc1g14dcktg4 sc70 dck 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 q3 sn74ahc1g14drlr sot-5x3 drl 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 q3 package materials information www.ti.com 29-sep-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74AHC1G14DBVr sot-23 dbv 5 3000 202.0 201.0 28.0 SN74AHC1G14DBVr sot-23 dbv 5 3000 180.0 180.0 18.0 SN74AHC1G14DBVr sot-23 dbv 5 3000 180.0 180.0 18.0 SN74AHC1G14DBVr sot-23 dbv 5 3000 180.0 180.0 18.0 SN74AHC1G14DBVrg4 sot-23 dbv 5 3000 180.0 180.0 18.0 SN74AHC1G14DBVt sot-23 dbv 5 250 180.0 180.0 18.0 SN74AHC1G14DBVt sot-23 dbv 5 250 180.0 180.0 18.0 SN74AHC1G14DBVt sot-23 dbv 5 250 180.0 180.0 18.0 sn74ahc1g14dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74ahc1g14dckr sc70 dck 5 3000 180.0 180.0 18.0 sn74ahc1g14dckrg4 sc70 dck 5 3000 180.0 180.0 18.0 sn74ahc1g14dckt sc70 dck 5 250 205.0 200.0 33.0 sn74ahc1g14dckt sc70 dck 5 250 180.0 180.0 18.0 sn74ahc1g14dckt sc70 dck 5 250 180.0 180.0 18.0 sn74ahc1g14dcktg4 sc70 dck 5 250 180.0 180.0 18.0 sn74ahc1g14drlr sot-5x3 drl 5 4000 202.0 201.0 28.0 package materials information www.ti.com 29-sep-2018 pack materials-page 2

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

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